WP4: Micro-electronics and interconnections


  • Deliver CLICPIX and ATLAS/CMS 65 nm CMOS readout chips for planar, 3D and HV-CMOS pixel sensors 
  • Share expertise on TSMC 65 nm CMOS and coordinate developments with CERN RD53 R&D program on microelectronics for pixels
  • Select best SiGe 130/180 nm process for high speed/high dynamic range ASIC design to upgrade current SiGe 350 nm AMS process
  • Deliver SPIROC3 SiPM readout chip for calorimeter readout and RPC high timing readout chip 
  • Produce through-silicon vias (TSV) on 65 nm CMOS wafers and connect 65 nm chips with and without TSVs to pixel sensors


  • Task 4.1 Scientific coordination
  • Task 4.2 65 nm microelectronics 
  • Task 4.3 SiGe 130/180 nm microelectronics
  • Task 4.4 Interconnections


Del. no. Deliverable name WP no. Planned delivery date Actual delivery date Status  Comments
D4.1 CMOS 65 nm engineering run 4 M36 09/04/2018 Achieved Report
D4.2 BICMOS SiGe engineering run 4 M36 09/04/2018 Achieved Report
D4.3 Through Silicon Vias production 4 M54      


Mil. no. Milestone name WP no. Planned delivery date Actual delivery date Status Comments
MS21 Architectural review of deliverable chips in 65nm run 4 M14 12/07/2016 Achieved Report
MS22 Selection of SiGe foundry 4 M14 12/07/2016 Achieved Report
MS23 Selection of TSV process 4 M14 15/07/2016 Achieved Report
MS63 Final design review of 65nm CMOS chips 4 M30 23/10/2017 Achieved Report
MS64 Final design review of deliverable chips in SiGe run 4 M30 18/10/2017 Achieved Report
MS65 Final design review of deliverable D4.3 4 M30 30/10/2017 Achieved Report
MS95 Test report of deliverable D4.1 4 M46 28/02/2019 Achieved Report
MS96 Test report of deliverable D4.2 4 M46      
MS97 Test report of deliverable D4.3 4 M46 M58 Delayed Justification for delay


The list of WP4 publications can be found in CDS. 

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